1. Field of the Invention
The present invention relates to a semiconductor storage apparatus that includes a nonvolatile memory cell, and also relates to a readout method for such storage apparatus.
2. Description of the Related Art
Japanese Patent Kokai (Laid-open publication) No. 2000-306392 discloses a semiconductor storage apparatus which includes an MROM (Mask Read-Only Memory) as a nonvolatile memory. This semiconductor storage apparatus has an array of NAND-type memory cells and a current detection-type sense amplifier, as shown in FIG. 7 of the accompanying drawings. The array of NAND-type memory cells includes two types (NMOS and DMOS) of transistors with different on resistances and threshold values to hold individual bits of stored data. The memory cell array includes a plurality of data cells arranged in an array. Data cells are selected by word lines (WL) which specify rows, and control gates (CG) which specify columns.
Readout of stored data from such a semiconductor storage apparatus is generally carried out as follows: when a certain word line is selected, the data cells of the data cell portion of the column selected by the control gate and the data cell of the reference cell portion for reference potential generation are simultaneously selected. Then, a reference voltage Vref occurs in a reference potential generation circuit due to a reference current Iref flowing from the reference cell portion. By comparing this reference voltage Vref with a voltage obtained by amplifying, in a data detection circuit, the cell current Icell flowing from the data cell portion, the output data Vsa is produced.
Such NAND-type memory cells include NMOS transistors which are ordinary N-channel transistors adapted to store “L” data, and DMOS transistors which are depletion-type transistors adapted to store “H” data. A DMOS transistor has a threshold Vt lower than an ordinary NMOS transistor, and is in the on state whether the gate voltage is H (high) or L (low). The transistor on resistance is higher for an NMOS than for a DMOS transistor. Because the on resistance of the DMOS transistor is lower, the greater the number of DMOS transistors among a plurality of data cells connected on the same bit line, the lower is the total series resistance of the bit line. A larger cell current flows when the total series resistance of the bit line is smaller.
Hence, some of the columns selected through control of the control gate may differ from other columns in the cell current flowing in the bit line even when the “H” readout is equally performed on these columns. Also, when the current is large, overshoot or undershoot may occur in the “H” output, resulting in erroneous data output or in access delays, as shown in FIG. 8 of the accompanying drawings.
In FIG. 8, Rcdv SMALL indicates when the resistance Rcdv is small, and Rcdv LARGE indicates when the resistance Rcdv is large. The vertical axis of the graph (FIG. 8) indicates Icell[μA] which his a cell current with the unit of μA. μA is micro-ampere. The horizontal axis of the graph (FIG. 8) indicates VCC[V] which is a voltage to be supplied to the cell, with the unit of V. V is volt. Icell 16DMOS represents the cell current flowing when the data cell portion includes sixteen DMOSs, and Icell 1DMOS represents the cell current flowing when the data cell portion includes a single DMOS. CURRENT DIFFERENCE LARGE indicates that the difference between the Icell 16 DMOS and Icell 1DMOS is large, and CURRENT DIFFERENCE SMALL indicates that the difference between the Icell 16DMOS and Icell 1DMOS is small.
A method of overcoming this difficulty is known. It employs a resistance Rcdv which sets the cell supply voltage CELLVCC to an arbitrary level through the voltage drop across the resistance. The resistance Rcdv greatly reduces the maximum cell current, and the minimum cell current declines gradually compared with the maximum cell current, as shown in FIG. 9 of the accompanying drawings. That is, the resistance Rcdv reduces the difference between the minimum cell current and the maximum cell current.
In FIG. 9, UNDERSHOOT indicates where the undershoot occurs, and DISCHARGE DELAY indicates where the discharge delay occurs.